A tiered semiconductor structure, such as a stacked CMOS structure, comprises a plurality of tiers within which semiconductor devices, such as PMOS or NMOS devices, are formed. In an example, a first tier comprises a first structure of a semiconductor device and a second tier comprises a second structure of the semiconductor device. A via is used to connect the first structure to the second structure. Because tier-to-tier vias are relevantly small, such as a via having a diameter less than 0.3 μm, misalignment, incomplete tunneling, or over tunneling can occur during a stacking process, such as a CMOS stacking process, that results in stacking system yield loss or other penalties.